1. Technical Field
The present invention relates to a thermal infrared solid-state imaging device for detecting a temperature change generated by an incident infrared ray with two-dimensionally arrayed sensors, and more particularly to a thermal infrared solid-state imaging device that integrates electric signals from the sensors with a signal processing circuit, and then outputs the integrated signal.
2. Related Art
A circuit of an infrared solid-state imaging device making use of a temperature depending characteristic of a forward voltage of a diode driven at a constant current is disclosed, for example, in JP 2003-222555 A. FIG. 8 shows a configuration of the infrared solid-state imaging device disclosed in JP 2003-222555 A.
For a solid-state imaging device, the uniformity of characteristics among pixels is important. A diode is very small in fluctuations of forward voltage or temperature dependence among pixels, and it is particularly effective for enhancing the characteristic uniformity. A plurality of diodes 801 each having a thermally insulating structure serving as infrared detector (three in an example in FIG. 8) are connected in series for ensuring the sensitivity. The diodes 801 are arrayed two-dimensionally (4 rows×4 columns in the example in FIG. 8) to compose a pixel array. In each row, the anode of the diode 801 of each pixel is commonly connected by a horizontal drive line 802, and in each column, the cathode of the diode 801 of each pixel is commonly connected by a vertical signal line 807. By a vertical scanning circuit 806 and switches 803, 8031, . . . , the horizontal drive lines 802 of the individual rows are connected sequentially to a vertical power supply line 804. As a result, a power supply voltage is supplied to the diode 801 of the selected row from a power supply terminal 805. In JP 2003-222555 A, a constant current source 808 is connected to a terminal end of the vertical signal line 807 connected to the cathode side of the diode 801, and hence the diode 801 is driven at a constant current. The voltage across the constant current source 808 is integrated and amplified in an integrating circuit 809, and is sequentially output to an output terminal 812 by means of a horizontal scanning circuit 810 and a switch 811.
The current flowing in the horizontal drive lines 802 decreases gradually as going toward the right end of the pixel area, and thus a voltage distribution occurs among columns in the drive lines. Accordingly, in JP 2003-222555 A, a bias line 819 having the same resistance of the horizontal drive line 802 is disposed near the integrating circuit 809, and a second current source 820 for providing the same current of the current source 808 is disposed in each pixel column. Hence, simulating the voltage distribution in the horizontal drive line 802, the voltage of the bias line 819 and the voltage of the vertical signal line 807 are differentially integrated by the integrating circuit 809, so that saturation of the integrating circuit 809 by voltage drop distribution in the horizontal drive line 802 and other troubles can be prevented, and a necessary degree of amplification may be assured.
Moreover, provided is a reference signal output circuit 813 which is driven at a constant current by a current source 815, and includes a diode 814 not having a thermally insulating structure. The bias line 819 is provided with a voltage by way of low pass filters 816, 818 and a buffer 817 on the basis of the voltage of the reference signal output circuit 813. Thus, an infrared solid-state imaging device having small temperature drift is realized.
However JP 2003-222555 A does not consider the output distribution due to voltage distribution (fluctuations) caused by resistances of the vertical power supply line 804 and the vertical signal line 807. Response of a thermal infrared solid-state imaging device to an infrared ray, that is, change in voltage across a pixel is very small as compared with voltage drop components in the vertical power supply line 804 and the vertical signal line 807. Accordingly, when a voltage distribution occurs in the taken image due to resistance of the vertical power supply line 804 and the vertical signal line 807, the amplifying circuit 809 is saturated by this voltage drop distribution as well as other problem, so that a necessary amplification factor may not be assured.
Referring now to FIG. 9, the voltage distribution due to resistances of the vertical power supply line 804 and the vertical signal line 807 is discussed. FIG. 9 is a diagram of showing explicitly resistance in each pixel pitch of the horizontal drive line 802, the vertical power supply line 804, and the vertical signal line 807 in the circuit shown in FIG. 8. In FIG. 9, a second row from the bottom is energized, and the path of the flowing current is indicated by broken lines. For the sake of simplicity of explanation, the pixel array is composed of four rows by four columns, and the energized diodes of the second row from the bottom are shown in blank triangle. Also for the sake of simplicity of explanation, the integrating circuit 809 has a single input, and only one diode is included in a pixel. In FIG. 9, resistance in each pixel pitch of the vertical power supply line 804, the horizontal drive line 802, and the vertical signal line 807 are respectively denoted as Rb, Rd, and Rs. In design, the horizontal drive line 802 has the same layout between the rows, and the vertical signal line 807 is same in layout between the columns.
Values of Rd are same between the rows and values of Rs are same between the columns. The current of the current source 808 is supposed to be I. When the second row from the bottom is energized, a current 4I, which is a value obtained by multiplexing a current I by the number (four) of pixels in the horizontal direction, flows in the vertical power supply line 804, while a current I flows in the vertical signal line 807. Therefore, when the second row from the bottom is energized, a voltage drop ΔVv2 in the wiring in the vertical direction is expressed in the following equation.ΔVv2=Rb·4I+2Rs·I  (1)
Similarly, when a third row from the bottom is energized, a voltage drop ΔVv3 in the wiring in the vertical direction is expressed in the following equation.ΔVv3=2Rb·4I+Rs·I  (2)
Similarly, when fourth and first rows from the bottom are energized, voltage drops ΔVv4 and ΔVv1 in the wiring in the vertical direction are expressed in the following equations.ΔVv4=3Rb·4I  (3)ΔVv1=3Rs·I  (4)
By applying the aforementioned relation to a pixel array of M rows×N columns, when an m-th row from the bottom is energized, a voltage drop ΔVvm in the wiring in the vertical direction is expressed in the following equation.
                                                                        Δ                ⁢                                                                  ⁢                Vvm                            =                            ⁢                                                                    (                                          m                      -                      1                                        )                                    ·                  Rb                  ·                  NI                                +                                                      (                                          M                      -                      m                                        )                                    ·                  Rs                  ·                  I                                                                                                        =                            ⁢                                                m                  ·                                      (                                                                  N                        ·                        Rb                                            -                      Rs                                        )                                    ·                  I                                -                                  m                  ·                  Rb                  ·                  N                  ·                  I                                +                                  M                  ·                  Rs                  ·                  I                                                                                        (        5        )            
Therefore, regardless of the row to be energized, in order to make uniform the voltage drop ΔVvm in the wiring in the vertical direction, the condition is expressed as follows.N·Rb=Rs  (6)
That is, it is necessary to determine the layout of the vertical power supply line 804 and the vertical signal line 807 so as to satisfy the relation of equation (6). However, according to the diagram, the vertical power supply line 804 and the vertical signal line 807 are different in the peripheral circuit, that is, the peripheral layout, and Rb and Rs per unit length do not change always at the same rate because of the process variations, so that it is difficult to satisfy the relation of equation (6) strictly by the layout only. In particular, when the number of pixels is great, even if a slight variation occurs in Rb and Rs, the difference in the voltage drop between the vertical power supply line 804 and the vertical signal line 807 becomes large. In addition, the difference is further amplified in the integrating circuit 509, so that a larger distribution in the element output may occur.